Avalon Memory-Mapped Interfaces.

Avalon MM Interface

1. IP 블록 및 peripherals 간 데이터 교환 단순화 / 호환성

2. Burst transfer 데이터 연속 전송(처리량 최적화)

3. FPGA, SoC에 통합하여 시스템 구축

4. 실시간 응답, 동기화를 제공하여 IP 블록 간 안정적인 데이터 전송 가능

> 데이터 전송 간소화 및 데이터 흐름의 효율적인 관리

> Design complexity와 개발 프로세스의 단순화

 

Avalon Data-Bus < Data Transfer

1. Data Bit 동시 전송

1-1. 동시 전송으로 시간 절약

1-2. 전송 속도 향상

1-3. 데이터 무결성(일괄 처리) 및 리소스 최소화

2. 동시성 및 병렬 처리로 성능 향상

> 데이터를 효과적으로 처리

 

Using Data-Bus > Interface 최적화 > peripherals, IP 블록 간 Data Flow 효율적 관리 가능

---

Avalon Memory-Mapped System

 

interconnect : Data / Address routing, Data Priority, System Scalability(IP, Peripherals etc.)

 

 

Slave Interface : Only responds to write Signal.

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Read and Write Transfer.

Read	1	M > S : address, byteenable, read signal asserted. M < S : waitrequest asserted and stalling the transfer.
	2	waitrequest asserted, the cycles becomes a wait-state. address, byteenable, read, write signal remain constant.
	3	waitrequest deasserted(slave) slave asserts readdata, reponse.
	4	waitrequest deasserted(master) and completing the transfer. master samples readdata, response.
Write	5	M > S : address, byteenable, write, writedata signal asserted. M < S : waitrequest asserted and stalling the transfer.
	6	waitrequest deasserted(slave)
	7	M > S : master write data, slave capture writedata and ending the transfer.

 

Read : (1) Master가 Slave에게 Address, byteenable, read 를 전달하면 (2) waitrequest가 지나고 (3) Slave는 Master가 요청한 주소의 Data를 read하고 readdata를 Master로 반환한다. (4) Master는 readdata를 읽고 전송을 끝낸다. 

---

Avalon Model (Only for Simulation)

Master > Slave : address, byteenable, read, write, writedata

Slave > Master : readdata, waitrequest

`timescale 1ns/1ns
// Avalon Bus Model for Simulation, Master
module avalon_model ( 
    input             clk       ,
    input             rst       ,
    output reg [31:0] mp_addr   , 
    output reg [ 3:0] mp_bEn    , 
    output reg        mp_rD     , 
    output reg        mp_wR     , 
    input             mp_waitR  , 
    input      [31:0] mp_rData  ,
    output reg [31:0] mp_wData   
);
endmodule

Use task(Bus Modeling) function for Read / Write transfer.

    parameter FF = 1; // 1ns delay

    task avalon_read;
        input [31:0] r_address;
        input [ 3:0] r_byteenable;
        begin
            @(posedge clk);
            #(FF);
            address    = r_address;
            byteenable = r_byteenable;
            read       = 1'b1;
            @(posedge clk);
            while (waitrequest) begin
                @(posedge clk);
            end 
            $display("Aavalon r_address %d, readdata %d", address, readdata);
            #(FF);
            address    = 32'hx;
            byteenable = 4'bx;
            read       = 1'b0; 
        end
    endtask

    task avalon_write;
        input [31:0] w_address;
        input [31:0] w_writedata;
        begin
            #(FF);
            address    = w_address;
            byteenable = 4'b0001;
            write      = 1'b1;
            writedata  = w_writedata;
            @(posedge clk);
            while(waitrequest)begin
                @(posedge clk);
            end
            #(FF);
            address    = 32'hx;
            byteenable = 4'bx;
            read       = 1'b0;
            write      = 1'b0;
            writedata  = 32'hx;
            @(posedge clk);
        end
    endtask

    initial begin
        address    = 32'hx;
        byteenable = 4'bx;
        read       = 1'b0;
        write      = 1'b0;
        writedata  = 32'hx;
        
        repeat(3) @(posedge clk);
        
        // address, byteenable hard coding 
        avalon_write(32'h0000, 32'hf); //address, writedata
        avalon_write(32'h0001, 32'h8);
        avalon_read(32'h0002, 4'b0001);
        avalon_read(32'h0003, 4'b0011);
    end

 

//testbench

`timescale 1 ns / 1 ns

module tb_EX_avalon_model();
    reg            clk;
    reg            reset;
    wire  [31:0]   address;
    wire  [ 3:0]   byteenable;
    wire           read;
    wire           write;
    reg            waitrequest;
    reg   [31:0]   readdata;
    wire  [31:0]   writedata;
);

    parameter FF = 1;
    
    EX_avalon_model uEX_avalon_model_0 (
        .clk         (clk        ),
        .reset       (reset      ),
        .address     (address    ),
        .btyeenable  (byteenable ),
        .read        (read       ),
        .write       (write      ),
        .waitrequest (waitrequest),
        .readdata    (readdata   ),
        .writedata   (writedata  )
    );
    
    initial fork
        clk_task();
        reset_task();
        readdata_task();
    join
    
    task clk_task;
        begin
            clk = 1'b0;
            forever #10 clk = ~clk;
        end
    endtask
    
    task reset_task;
        begin
            reset = 1'b0;
            repeat(1) @(posedge clk);
            reset = 1'b1;
            repeat(1) @(posedge clk);
            reset = 1'b1;
        end
    endtask
    
    //readdata hard coding
    task readdata_task;
        begin
            readdata = 32'hx;
            repeat(8) @(posedge clk);
            readdata = 32'h000000AC;
            @(posedge clk);
            readdata = 32'hx;
            @(posedge clk);
            readdata = 32'h0000ACAC;
            @(posedge clk);
            readdata = 32'hx;
        end
    endtask
    
endmodule

 

Modelsim Simulation

[Write]

address 0000, 0001 에 32'hf와 32'h8 data를 write

[Read]

Master : address, byteenable, read 신호를 Slave에 요청

Slave : 해당 address의 data를 read하고 readdata를 Master로 반환

1. address = 32'h0002, byteenable = 4'b0001 > read address 32'h0002's data  00 00 00 AC

2. address = 32'h0003, byteenable = 4'b0011 > read address 32'h0003's data  00 00 AC AC