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[Harman] 반도체 설계/Avalon

Avalon Memory-Mapped Interfaces - Register.

Block Diagram

 

Master > Slave Slave > Master My_reg
mp_addr
mp_bEn
mp_rD
mp_wR
mp_wData
mp_rData
mp_waitR
addr
bEn
rD
wR
wData

waitR
rData

rMy_reg

 

My_reg Implementation.

 

avalon_model

Test-Bench

 

Tcl

 

Simulation waveform

mp_writedata > my_reg > mp_readdata = rData

 

 

Board Verification > niosII.qsys

Add Custom Logic

My_reg_0  Base address : 0x0000_1088

 

Nios II Console