Quartus II Project - mux4, shifter

1. mux4

 - Build a 4-bit 2:1 multiplexer using the if-else statement

 - Synthesize and verify its operation

 

Following information.

a. The multiplexer has two 4-bit data inputs, a select line and a 4-bit output.

b. Describe the following behavior :

 - if mux_sel is 0, then choose mux_in_a for mux_out.

 - if mux_sel is 1, then choose mux_in_b for mux_out.

c. Use the names in the diagram above to name your block and its port (all lower-case)

 - mux4, [3:0]mux_in_a, [3:0]mux_in_b, mux_sel, mux_out

d. Coding with behavioral statements requires using a precedrual (e.g. always)

 

 

If the behavior statement is 1 line, begin ~end can be omitted.

 

 

Test-bench simulation (modelsim)

 

 

 

2. shifter

 - Build a 8-bit to 16-bit left shifter using the if-else statement

 - Synthesize and verify its operation

 

Following information.

a. The multiplexer has one 8-bit data inputs, a control line and a 16-bit output.

b. Describe the following behavior :

 - When shift_cntrl is 0 or 3, then no shift (i.e. [7:0]shift_out equals [7:0]inp ; all other bits '0')

 - When shift_cntrl is 1, then shift input to the left by 4 bits within shift_out (i.e. [11:4]shift_out equals [7:0]inp ; all other bits '0')

 - When shift_cntrl is 2, then shift input to the left by 8 bits within shift_out (i.e. [15:8]shift_out equals [7:0]inp ; all other bits '0')

c. Use the names in the diagram above to name your block and its port (all lower-case)

 - mux4, [3:0]mux_in_a, [3:0]mux_in_b, mux_sel, mux_out

d. Coding with behavioral statements requires using a precedrual (e.g. always)

 

[1] shifting operator, sensitivity list

 

 

a | b : bitwise operator

a || b : logical operator

<< a : shift a-bit to the left

>> b : shift b-bit to the right

 

[2] direct assignment, all 

 

 

{  } : Concatenate

shift_cntrl 1 : { 4'h0, inp, 4'h0 } : 0 xx 0 // shift to the left 4-bit

shift_cntrl 2 : { inp, 8'h00 } : xx 00 // shift to the left 8-bit

shift_cntrl 0 or 3 : { 8'h00, inp } : 00 xx // no shift

 

Test-bench simulation. (modelsim)

 

 

[7:0] inp - 8'hf4

[15:0] shift_out - 16'hxxxx

shift_cntrl : 0 (2'd0), shift_out : 16'h  00  f4  (no shift)

shift_cntrl : 1 (2'd1), shift_out : 16'h  0 f4 0  (4-bit shift to the left)

shift_cntrl : 2 (2'd2), shift_out : 16'h  f4  00  (8-bit shift to the left)

shift_cntrl : 3 (2'd3), shift_out : 16'h  00  f4  (no shift)