[Vivado] 03. Adder 8bit

Half Adder.

module half_adder ( 
    input i_a,
    input i_b,
    output o_sum,
    output o_carry
);
    
    assign o_sum = i_a ^ i_b;
    assign o_carry = i_a & i_b;
    
endmodule

Full Adder 1 bit.

module full_adder_1bit (
   input i_a,
   input i_b,
   input i_cin,
   output o_sum,
   output o_carry    
 );   
 
 wire w_sum1, w_carry1, w_carry2;
 
 half_adder U_HA_0 ( 
    .i_a(i_a),
    .i_b(i_b),
    .o_sum(w_sum1),
    .o_carry(w_carry1)
);

half_adder U_HA_1 ( 
    .i_a(w_sum1),
    .i_b(i_cin),
    .o_sum(o_sum),
    .o_carry(w_carry2)
);

assign o_carry = w_carry1 | w_carry2;

endmodule

Full Adder 4 bit.

module full_adder_4bit (
   input [3:0]i_a,
   input [3:0]i_b,
   input i_cin,
   output [3:0]o_sum,
   output o_carry   
);

wire w_c1, w_c2, w_c3;

full_adder_1bit U_FA_0 (
    .i_a(i_a[0]),
    .i_b(i_b[0]),
    .i_cin(i_cin),
    .o_sum(o_sum[0]),
    .o_carry(w_c1)
);

full_adder_1bit U_FA_1 (
    .i_a(i_a[1]),
    .i_b(i_b[1]),
    .i_cin(w_c1),
    .o_sum(o_sum[1]),
    .o_carry(w_c2)
);

full_adder_1bit U_FA_2 (
    .i_a(i_a[2]),
    .i_b(i_b[2]),
    .i_cin(w_c2),
    .o_sum(o_sum[2]),
    .o_carry(w_c3)
);

full_adder_1bit U_FA_3 (
    .i_a(i_a[3]),
    .i_b(i_b[3]),
    .i_cin(w_c3),
    .o_sum(o_sum[3]),
    .o_carry(o_carry)
);    

endmodule

Adder 8 bit.

`timescale 1ns / 1ps

module adder_8bit (
    input [7:0] i_a,
    input [7:0] i_b,
    output [7:0] o_sum,
    output o_carry
);

wire w_c4;

full_adder_4bit U_FA4_0 (
    .i_a(i_a[3:0]),
    .i_b(i_b[3:0]),
    .i_cin(0),
    .o_sum(o_sum[3:0]),
    .o_carry(w_c4)
 );
 
 full_adder_4bit U_FA4_1 (
    .i_a(i_a[7:4]),
    .i_b(i_b[7:4]),
    .i_cin(w_c4),
    .o_sum(o_sum[7:4]),
    .o_carry(o_carry)
 );
 
 endmodule