전체 글 (143) 썸네일형 리스트형 AXI4 Bus Interface bus_slv.v // shift + scroll module bus_slv ( input wire clk_axi_slv , input wire rstb_slv , input wire [ 1:0] i_axi4_slv_awid___ , input wire [ 31:0] i_axi4_slv_awaddr_ , input wire [ 7:0] i_axi4_slv_awlen__ , input wire [ 2:0] i_axi4_slv_awsize_ , input wire i_axi4_slv_awv.. Pulse Generator. module pulse_gen_en ( input clk , input rstb , input en_s , // using enable = 1 input en , // enable signal input input in , output out ); reg in_dly0; reg in_dly1; always@(posedge clk or negedge rstb) if(~rstb) begin in_dly0 SPI Interface. SPI Interface. `timescale 1 ns / 1 ps module task_spi ( // SPI master in out ports input i_spi_miso , output o_spi_clk , output o_spi_csn , output o_spi_wex , output o_spi_mosi ); localparam SPI_PER = 300; reg spi_clk; reg spi_csn; reg spi_wex; reg spi_mosi; reg [7:0] sp onlyiknowabout.tistory.com `timescale 1 ns / 1 ps module task_spi ( // SPI master in out ports input i_spi_miso , output o_spi.. sys_sync_gen module sys_sync_gen ( // clock reset input wire sys_clk , input wire rstb , // sync , de output reg hsync , output reg vsync , output reg de ); // parameter define localparam HS_IDLE = 2'd0 ; localparam HS_BP = 2'd1 ; localparam HS_ACTV = 2'd2 ; localparam HS_FP = 2'd3 ; localparam VS_IDLE = 2'd0 ; localparam VS_BP = 2'd1 ; localparam VS_ACTV = 2'd2 ; localparam VS_FP = 2'd3 ; localparam HBP = 1.. Image processing filter design. 보호되어 있는 글입니다. MIPI specification. 보호되어 있는 글입니다. Linux. 보호되어 있는 글입니다. Verilog Projects. 1. 8x8 Multiplier 2. UART 3. Avalon Bus Modeling 4. Avalon Bus : PWM 5. Avalon Bus : GPIO 8-Bit Multiplier. Development Environment. Program : Quartus Prime 18.1 Lite Edition Tool : Modelsim 10.5b Starter Edition FPGA : MAX10 Grammer : Verilog2001 Objective. Design an 8-bit Multiplier module in Verilog and verify the results through simulation. Why? ALU는 CPU onlyiknowabout.tistory.com UART. Deve.. 이전 1 2 3 4 ··· 18 다음
