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[Harman] 반도체 설계/Quartus

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Quartus II Project - notes [2] Always / Initial Blocks (Procedural Assignments) 1. initial - each 'initial' blocks executes concurrently starting at time 0. - executes only 'once' and does not execute again. module system; reg a, b, c, d; // single statement initial a = 1'b0; // time 0 : power ON initial begin b = 1'b1; #5 c = 1'b0; #10 d = 1'b0; end initial #20 $finish; endmodule 2. always - each 'always' blocks executes con..
Quartus II project - notes [1]
Quartus II project - Simple Uart Tx. BPS : 115200 DE1-SoC Board default Frequency : 50Mhz [20ns] 1/115200 = 0.00000868s = 0.00868ms = 8.68us = 8680ns [1bit] need to maintain 434 cycles to make 8680ns. // 434 counter = 8680ns reg [3:0] cst; //idle ~ stop_1, 12 state reg [3:0] nst; reg [8:0] clk_count; // 512, 9bit always @(posedge clk, negedge reset_n) begin if(!reset_n) begin // active low clk_count
Quartus II Project - fnd counter module fnd_counter ( input clk, input reset_n, output seg_a, seg_b, seg_c, seg_d, seg_e, seg_f, seg_g ); wire w_clk; wire [3:0] w_cnt; sec_tick_gen uSec_tick_gen ( .clk(clk), .reset(reset_n), .o_clk(w_clk) ); data_gen uData_gen ( .tick(w_clk), .reset_n(reset_n), .cnt(w_cnt) ); seven_segment_cntrl uSeven_segment_cntrl ( .inp(w_cnt), .seg_a(seg_a), .seg_b(seg_b), .seg_c(seg_c), .seg_d(seg_d), .seg..
Quartus II Project - adder, mult4x4 1. adder - Build a 16-bit adder using the '+' operator - Practice coding basic module structure Continuous Assignment. - assign sum 2. mult4x4 - Build a 4x4 multiplier block using the '* operator - Synthesis and verify its operation
Quartus II Project - mux4, shifter 1. mux4 - Build a 4-bit 2:1 multiplexer using the if-else statement - Synthesize and verify its operation Following information. a. The multiplexer has two 4-bit data inputs, a select line and a 4-bit output. b. Describe the following behavior : - if mux_sel is 0, then choose mux_in_a for mux_out. - if mux_sel is 1, then choose mux_in_b for mux_out. c. Use the names in the diagram above to name ..

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